&soc {
	mdss_dsi0_pll: qcom,mdss_dsi0_pll {
		compatible = "qcom,mdss_dsi_pll_7nm_v4_1";
		label = "MDSS DSI 0 PLL";
		cell-index = <0>;
		#clock-cells = <1>;
		reg = <0xae94900 0x280>,
		      <0xae94400 0x800>,
		      <0xaf03000 0x8>,
		      <0xae94200 0x100>;
		reg-names = "pll_base", "phy_base", "gdsc_base",
				"dynamic_pll_base";
		clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
		clock-names = "iface_clk";
		clock-rate = <0>;
		memory-region = <&dfps_data_memory>;
		qcom,dsi-pll-ssc-en;
		qcom,dsi-pll-ssc-mode = "down-spread";
	};

	mdss_dsi1_pll: qcom,mdss_dsi1_pll {
		compatible = "qcom,mdss_dsi_pll_7nm_v4_1";
		label = "MDSS DSI 1 PLL";
		cell-index = <1>;
		#clock-cells = <1>;
		reg = <0xae96900 0x280>,
		      <0xae96400 0x800>,
		      <0xaf03000 0x8>,
		      <0xae96200 0x100>;
		reg-names = "pll_base", "phy_base", "gdsc_base",
				"dynamic_pll_base";
		clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
		clock-names = "iface_clk";
		clock-rate = <0>;
		qcom,dsi-pll-ssc-en;
		qcom,dsi-pll-ssc-mode = "down-spread";
	};
	 mdss_dp_pll: qcom,mdss_dp_pll@c011000 {
		compatible = "qcom,mdss_dp_pll_7nm_v2";
		label = "MDSS DP PLL";
		cell-index = <0>;
		#clock-cells = <1>;

		reg =   <0x088ea000 0x200>,
			<0x088eaa00 0x200>,
			<0x088ea200 0x200>,
			<0x088ea2c0 0x8>,
			<0x088ea2c8 0x4>,
			<0x088ea600 0x200>,
			<0x088ea6c0 0x8>,
			<0x088ea6c8 0x4>,
			<0xaf03000 0x8>;
		reg-names = "pll_base", "phy_base",
			"ln_tx0_base", "ln_tx0_tran_base", "ln_tx0_vmode_base",
			"ln_tx1_base", "ln_tx1_tran_base", "ln_tx1_vmode_base",
			"gdsc_base";

		clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
			<&rpmhcc RPMH_CXO_CLK>,
			<&gcc GCC_DISP_AHB_CLK>,
			<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
		clock-names = "iface_clk", "ref_clk_src",
			"gcc_iface", "pipe_clk";
		clock-rate = <0>;
	};

};
